1. Field of the Invention
The present invention relates to a magnetic tunnel junction device and a method of manufacturing the same, particularly to a magnetic tunnel junction device with a high magnetoresistance and a method of manufacturing the same.
2. Description of Related Art
Magnetoresistive random access memories (MRAMs) refer to a large-scale integrated memory circuit that is expected to replace the currently widely used DRAM memories. Research and development of MRAM devices, which are fast and non-volatile memory devices, are being extensively carried out, and sample products of a 4 Mbit MRAM have actually been delivered.
FIGS. 8(A) and 8(B) show the structure and operation principle of a magnetic tunnel junction device (to be hereafter referred to as a “MTJ device”), which is the most important part of the MRAM. As shown in FIG. 8(A), a MTJ device comprises a tunnelling junction structure in which a tunnel barrier (to be hereafter also referred to as a “barrier layer”) made of an oxide is sandwiched between a first and a second electrode made of a ferromagnetic metal. The tunnel barrier layer comprises an amorphous Al—O layer (see Non-Patent Document 1). As shown in FIG. 8(A), in the case of parallel magnetization alignment where the directions of magnetizations of the first and second ferromagnetic electrodes are aligned parallel, the electric resistance of the device with respect to the direction normal to the interfaces of the tunneling junction structure decreases. On the other hand, in the case of antiparallel magnetization alignment where the directions of magnetizations of the first and second ferromagnetic electrodes are aligned antiparallel as shown in FIG. 8(B), the electric resistance with respect to the direction normal to the interfaces of the tunneling junction structure increases. The resistance value does not change in a general state, so that information “1” or “0” can be stored depending on whether the resistance value is high or not. Since the parallel and antiparallel magnetization alignments can be stored in a non-volatile fashion, the device can be used as a non-volatile memory device.
FIG. 9 shows an example of the basic structure of the MRAM. FIG. 9(A) shows a perspective view of the MRAM, and FIG. 9(B) schematically shows a circuit block diagram. FIG. 9(C) is a cross-section of an example of the structure of the MRAM. Referring to FIG. 9(A), in an MRAM, a word line WL and a bit line BL are disposed in an intersecting manner, with an MRAM cell disposed at each intersection. As shown in FIG. 9(B), the MRAM cell disposed at the intersection of a word line and a bit line comprises a MTJ device and a MOSFET directly connected to the MTJ device. Stored information can be read by reading the resistance value of the MTJ device that functions as a load resistance, using the MOSFET. The stored information can be rewritten by applying a magnetic field to the MTJ device, for example. As shown in FIG. 9(C), an MRAM memory cell comprises a MOSFET 100 including a source region 105 and a drain region 103 both formed inside a p-type Si substrate 101, and a gate electrode 111 formed on a channel region that is defined between the source and drain regions. The MRAM also comprises a MTJ device 117. The source region 105 is grounded, and the drain is connected to a bit line BL via the MTJ device. A word line WL is connected to the gate electrode 111 in a region that is not shown.
Thus, a single non-volatile MRAM memory cell can be formed by a single MOSFET 100 and a single MTJ device 117. The MRAMs are therefore suitable where high levels of integration are required.
Non-Patent Document 1: D. Wang, et al.: Science 294 (2001) 1488.